1. Field
The following description relates to a semiconductor device and a fabricating method thereof, and, for example, to a semiconductor device having a super junction structure and a fabricating method of such a semiconductor device.
2. Description of Related Art
High voltage power devices are often used in power integrated circuit (IC) apparatuses for power conversion and in power control systems. A planar gate metal oxide semiconductor field effect transistor (MOSFET) is often used as a high voltage device. Such a planar gate semiconductor device is illustrated in FIGS. 5 and 6.
FIG. 5 illustrates an example of a conventional planar gate MOSFET, and FIG. 6 illustrates the distribution of electric field that may be formed between area A and area B in the planar gate MOSFET depicted in FIG. 5.
A cross-sectional structure of a unit cell of the conventional planar gate MOSFET is illustrated in FIG. 5. The on-resistance of the unit cell may be affected by components of the channel, the junction field effect transistor (JFET), an epilayer (drift region), the substrate and the like. The amount of internal pressure and the distribution of electric field in the conventional planar gate MOSFET are graphically illustrated in FIG. 6. As illustrated in the graph of FIG. 6, the distribution of electric field in a conventional planar gate MOSFET is determined by its depletion layer that is formed between a p body well and an n-epilayer due to a voltage that is applied to the drain when the gate voltage is equal to the source voltage.
Therefore, in the conventional planar gate MOSFET, the thickness and the dopant concentration of the epilayer are usually set to be larger than or equal to a predetermined value in order to obtain a favorable distribution of the electric field. As a result, it is difficult to set the resistance of the epilayer to be lower than or equal to a predetermined value. Due to the relationship between the resistance and the distribution of electric field, limits may be imposed on lowering the resistance of the epilayer.
In order to solve this problem, the use of a super junction structure has been proposed. An example of a semiconductor device having a super junction structure is illustrated in FIGS. 7 and 8.
FIG. 7 depicts a cross-sectional view illustrating an example of a structure of a semiconductor device having a super junction structure. FIG. 8 depicts a graph illustrating the distribution of electric field that is formed between areas A, B and C in the semiconductor device illustrated in FIG. 7.
As illustrated in FIG. 7, the super junction structure is similar to the gate and p body well structure of a typical MOSFET. However, in a super junction semiconductor device, additional structures may be present in the drift region under the p body well in order to obtain the super junction characteristic.
In a typical MOSFET, a depletion layer extends in a vertical direction when a voltage is applied to the drain. However, in a semiconductor device with a super junction, a depletion layer extends in both vertical and horizontal directions as illustrated in FIG. 8. In such a device, when charge quantities of two areas are equal to each other, both of n-type and p-type areas are completely depleted. Therefore, no net charge exists in the vertical direction; thus, the electric field is theoretically uniform in the vertical direction.
Therefore, if charges are completely balanced between pillars in the semiconductor device having a super junction structure, an electric field distribution obtained from the semiconductor device is proportional to depths of the pillars; this electric field distribution is different from that of a typical MOSFET. Also, the dopant concentration of an n-type pillar that is in a drift region may be increased to obtain a lower resistance.
Attempts have been made to obtain both a low on-resistance and a favorable electric field distribution by using a super junction structure as described above. However, in such a semiconductor device, if the dopant quantity in the p-type pillar is different from the dopant quantity in the n-type pillar, a breakdown voltage can be substantially lowered as illustrated in the graph of FIG. 9.
Accordingly, a method that does not substantially lower the breakdown voltage even when the dopant quantities in the n-type and p-type pillars are different from each other is desirable in obtaining a semiconductor device having a super junction structure.